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cyiv-51001-1.7 ? 2013 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. cyclone iv device handbook, volume 1 february 2013 feedback subscribe iso 9001:2008 registered 1. cyclone iv fpga device family overview altera?s new cyclone ? iv fpga device family exte nds the cyclone fpga series leadership in providing the market?s lowe st-cost, lowest-power fpgas, now with a transceiver variant. cyclone iv devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing ba ndwidth requirements while lowering costs. built on an optimized low-power process, the cyclone iv device family offers the following two variants: cyclone iv e?lowest power, high functionality with the lowest cost cyclone iv gx?lowest power and lowe st cost fpgas with 3.125 gbps transceivers 1 cyclone iv e devices are offered in core voltage of 1.0 v and 1.2 v. f for more information, refer to the power requirements for cyclone iv devices chapter. providing power and cost savings without sacrificing performance, along with a low-cost integrated transceiver option, cyclone iv devices are ideal for low-cost, small-form-factor applications in the wi reless, wireline, broadcast, industrial, consumer, and communi cations industries. cyclone iv device family features the cyclone iv device family of fers the following features: low-cost, low-power fpga fabric: 6k to 150k logic elements up to 6.3 mb of embedded memory up to 360 18 18 multipliers for dsp processing intensive applications protocol bridging applications for under 1.5 w total power february 2013 cyiv-51001-1.7
1?2 chapter 1: cyclone iv fpga device family overview cyclone iv device family features cyclone iv device handbook, february 2013 altera corporation volume 1 cyclone iv gx devices offer up to eight high-speed transceivers that provide: data rates up to 3.125 gbps 8b/10b encoder/decoder 8-bit or 10-bit physical media attachment (pma) to physical coding sublayer (pcs) interface byte serializer/deserializer (serdes) word aligner rate matching fifo tx bit slipper for common public radio interface (cpri) electrical idle dynamic channel reconfigur ation allowing you to change data rates and protocols on-the-fly static equalization and pre-emphas is for superior signal integrity 150 mw per channel power consumption flexible clocking structure to support multiple protocols in a single transceiver block cyclone iv gx devices offer dedicated hard ip for pci express (pipe) (pcie) gen 1: 1, 2, and 4 lane configurations end-point and root-port configurations up to 256-byte payload one virtual channel 2 kb retry buffer 4 kb receiver (rx) buffer cyclone iv gx devices offer a wide range of protocol support: pcie (pipe) gen 1 1, 2, and 4 (2.5 gbps) gigabit ethernet (1.25 gbps) cpri (up to 3.072 gbps) xaui (3.125 gbps) triple rate serial digital in terface (sdi) (up to 2.97 gbps) serial rapidio (3.125 gbps) basic mode (up to 3.125 gbps) v-by-one (up to 3.0 gbps) displayport (2.7 gbps) serial advanced technology attachment (sata) (up to 3.0 gbps) obsai (up to 3.072 gbps)
chapter 1: cyclone iv fpga device family overview 1?3 device resources february 2013 altera corporation cyclone iv device handbook, volume 1 up to 532 user i/os lvds interfaces up to 840 mbps transmitter (tx), 875 mbps rx support for ddr2 sdram interfaces up to 200 mhz support for qdrii sram and ddr sdram up to 167 mhz up to eight phase-locked loops (plls) per device offered in commercial and industrial temperature grades device resources table 1?1 lists cyclone iv e device resources. table 1?1. resources for the cyclone iv e device family resources ep4ce6 ep4ce10 ep4ce15 ep4ce22 ep4ce30 ep4ce40 ep4ce55 ep4ce75 ep4ce115 logic elements (les) 6,272 10,320 15,408 22,320 28,848 39,600 55,856 75,408 114,480 embedded memory (kbits) 270 414 504 594 594 1,134 2,340 2,745 3,888 embedded 18 18 multipliers 15 23 56 66 66 116 154 200 266 general-purpose plls22444444 4 global clock networks 10 10 20 20 20 20 20 20 20 user i/o banks 88888888 8 maximum user i/o (1) 179 179 343 153 532 532 374 426 528 note to table 1?1 : (1) the user i/os count from pin-out fil es includes all general purpo se i/o, dedicated clock pins, and dual purpose configuratio n pins. transceiver pins and dedicated configuration pins are not included in the pin count.
1?4 chapter 1: cyclone iv fpga device family overview device resources cyclone iv device handbook, february 2013 altera corporation volume 1 table 1?2 lists cyclone iv gx device resources. table 1?2. resources for the cyclone iv gx device family resources ep4cgx15 ep4cgx22 ep4cgx30 (1) ep4cgx30 (2) ep4cgx50 (3) ep4cgx75 (3) ep4cgx110 (3) ep4cgx150 (3) logic elements (les) 14,400 21,280 29,440 29,440 49,888 73,920 109,424 149,760 embedded memory (kbits) 540 756 1,080 1,080 2,502 4,158 5,490 6,480 embedded 18 18 multipliers 0 40 80 80 140 198 280 360 general purpose plls 1 2 2 4 (4) 4 (4) 4 (4) 4 (4) 4 (4) multipurpose plls 2 (5) 2 (5) 2 (5) 2 (5) 4 (5) 4 (5) 4 (5) 4 (5) global clock networks 20 20 20 30 30 30 30 30 high-speed transceivers (6) 24448888 transceiver maximum data rate (gbps) 2.5 2.5 2.5 3.125 3.125 3.125 3.125 3.125 pcie (pipe) hard ip blocks 11111111 user i/o banks 9 (7) 9 (7) 9 (7) 11 (8) 11 (8) 11 (8) 11 (8) 11 (8) maximum user i/o (9) 72 150 150 290 310 310 475 475 notes to table 1?2 : (1) applicable for the f169 and f324 packages. (2) applicable for the f484 package. (3) only two multipurpose plls for f484 package. (4) two of the general purpose plls ar e able to support transceiver clocking. for more informatio n, refer to the clock networks and plls in cyclone iv devices chapter. (5) you can use the multipurpose pl ls for general purpose clocking when they are not used to cl ock the transceivers. for more in formation, refer to the clock networks and plls in cyclone iv devices chapter. (6) if pcie ? 1, you can use the remaining transceive rs in a quad for other protocols at the same or different data rates. (7) including one configuration i/o bank and two dedicated clock input i/o banks for hssi reference clock input. (8) including one configuration i/o bank and four dedicated clock input i/o banks for hssi reference clock input. (9) the user i/os count from pin-out fil es includes all general purpo se i/o, dedicated clock pins, and dual purpose configuratio n pins. transceiver pins and dedicated configuration pins are not included in the pin count.
chapter 1: cyclone iv fpga device family overview 1?5 package matrix february 2013 altera corporation cyclone iv device handbook, volume 1 package matrix table 1?3 lists cyclone iv e device package offerings. table 1?3. package offerings for the cyclone iv e device family (1) , (2) package e144 m164 m256 u256 f256 u484 f484 f780 size (mm) 22 22 8 8 9 x 9 14 14 17 17 19 19 23 23 29 29 pitch (mm) 0.5 0.5 0.5 0.8 1.0 0.8 1.0 1.0 device user i/o lvds (3) user i/o lvds (3) user i/o lvds (3) user i/o lvds (3) user i/o lvds (3) user i/o lvds (3) user i/o lvds (3) user i/o lvds (3) ep4ce69121????1796617966?????? ep4ce109121????1796617966?????? ep4ce15 81 18 89 21 165 53 165 53 165 53 ? ? 343 137 ? ? ep4ce227917????1535215352?????? ep4ce30????????????328124532224 ep4ce40??????????328124328124532224 ep4ce55??????????324132324132374160 ep4ce75??????????292110292110426178 ep4ce115 ? ? ??????????280103528230 notes to table 1?3 : (1) the e144 package has an expo sed pad at the bottom of the packag e. this exposed pad is a ground pad that must be connected to the ground plane of your pcb. use this expos ed pad for electrical connectivity and not for thermal purposes. (2) use the pin migration view window in pin planner of the quar tus ii software to verify the pin migration compatibility when yo u perform device migration. for mo re information, refer to the i/o management chapter in volume 2 of the quartus ii handbook . (3) this includes both dedicated and emulated lv ds pairs. for more information, refer to the i/o features in cyclone iv devices chapter.
1?6 chapter 1: cyclone iv fpga device family overview package matrix cyclone iv device handbook, february 2013 altera corporation volume 1 table 1?4 lists cyclone iv gx device package offeri ngs, including i/o and transceiver counts. table 1?4. package offerings for the cyclone iv gx device family (1) package n148 f169 f324 f484 f672 f896 size (mm) 11 11 14 14 19 19 23 23 27 27 31 31 pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0 device user i/o lvds (2) xcvrs user i/o lvds (2) xcvrs user i/o lvds (2) xcvrs user i/o lvds (2) xcvrs user i/o lvds (2) xcvrs user i/o lvds (2) xcvrs ep4cgx15 72 25 2 72 25 2 ? ? ? ? ? ? ? ? ? ? ? ? ep4cgx22 ? ? ? 72 25 2 150 64 4 ? ? ? ? ? ? ? ? ? ep4cgx30 ? ? ? 72 25 2 150 64 4 290 130 4 ? ? ? ? ? ? ep4cgx50 ? ? ? ? ? ? ? ? ? 290 130 4 310 140 8 ? ? ? ep4cgx75 ? ? ? ? ? ? ? ? ? 290 130 4 310 140 8 ? ? ? ep4cgx110 ? ? ? ? ? ? ? ? ? 270 120 4 393 181 8 475 220 8 ep4cgx150 ? ? ? ? ? ? ? ? ? 270 120 4 393 181 8 475 220 8 note to table 1?4 : (1) use the pin migration view window in pin planner of the quar tus ii software to verify the pin migration compatibility when yo u perform device migration. for more information, refer to the i/o management chapter in volume 2 of the quartus ii handbook . (2) this includes both dedicated a nd emulated lvds pairs. for mo re information, refer to the i/o features in cyclone iv devices chapter.
chapter 1: cyclone iv fpga device family overview 1?7 cyclone iv device family speed grades february 2013 altera corporation cyclone iv device handbook, volume 1 cyclone iv device family speed grades table 1?5 lists the cyclone iv gx devices speed grades. table 1?6 lists the cyclone iv e devices speed grades. table 1?5. speed grades for the cyclone iv gx device family device n148 f169 f324 f484 f672 f896 ep4cgx15 c7, c8, i7 c6, c7, c8, i7 ? ? ? ? ep4cgx22 ? c6, c7, c8, i7 c6, c7, c8, i7 ? ? ? ep4cgx30 ? c6, c7, c8, i7 c6, c7, c8, i7 c6, c7, c8, i7 ? ? ep4cgx50 ? ? ? c6, c7, c8, i7 c6, c7, c8, i7 ? ep4cgx75 ? ? ? c6, c7, c8, i7 c6, c7, c8, i7 ? ep4cgx110 ? ? ? c7, c8, i7 c7, c8, i7 c7, c8, i7 ep4cgx150 ? ? ? c7, c8, i7 c7, c8, i7 c7, c8, i7 table 1?6. speed grades for the cyclone iv e device family (1) , (2) device e144 m164 m256 u256 f256 u484 f484 f780 ep4ce6 c8l, c9l, i8l c6, c7, c8, i7, a7 ??i7n c8l, c9l, i8l c6, c7, c8, i7, a7 ?? ? ep4ce10 c8l, c9l, i8l c6, c7, c8, i7, a7 ??i7n c8l, c9l, i8l c6, c7, c8, i7, a7 ?? ? ep4ce15 c8l, c9l, i8l c6, c7, c8, i7 i7n c7n, i7n i7n c8l, c9l, i8l c6, c7, c8, i7, a7 ? c8l, c9l, i8l c6, c7, c8, i7, a7 ? ep4ce22 c8l, c9l, i8l c6, c7, c8, i7, a7 ??i7n c8l, c9l, i8l c6, c7, c8, i7, a7 ?? ? ep4ce30 ? ? ? ? ? ? c8l, c9l, i8l c6, c7, c8, i7, a7 c8l, c9l, i8l c6, c7, c8, i7 ep4ce40 ? ? ? ? ? i7n c8l, c9l, i8l c6, c7, c8, i7, a7 c8l, c9l, i8l c6, c7, c8, i7 ep4ce55 ? ? ? ? ? i7n c8l, c9l, i8l c6, c7, c8, i7 c8l, c9l, i8l c6, c7, c8, i7 ep4ce75 ? ? ? ? ? i7n c8l, c9l, i8l c6, c7, c8, i7 c8l, c9l, i8l c6, c7, c8, i7 ep4ce115 ? ? ? ? ? ? c8l, c9l, i8l c7, c8, i7 c8l, c9l, i8l c7, c8, i7 notes to table 1?6 : (1) c8l, c9l, and i8l speed grades are applicable for the 1.0-v core voltage. (2) c6, c7, c8, i7, and a7 speed grades ar e applicable for the 1.2-v core voltage.
1?8 chapter 1: cyclone iv fpga device family overview cyclone iv device family architecture cyclone iv device handbook, february 2013 altera corporation volume 1 cyclone iv device family architecture this section describes cyclone iv device architecture and contains the following topics: ?fpga core fabric? ?i/o features? ?clock management? ?external memory interfaces? ?configuration? ?high-speed transceivers (c yclone iv gx devices only)? ?hard ip for pci express (cyclone iv gx devices only)? fpga core fabric cyclone iv devices leverage the same core fa bric as the very successful cyclone series devices. the fabric consists of les, made of 4-input look up tables (luts), memory blocks, and multipliers. each cyclone iv device m9k memory block provides 9 kbits of embedded sram memory. you can configure the m9k blocks as single port, simple dual port, or true dual port ram, as well as fifo buffers or rom. they can also be configured to implement any of the data widths in table 1?7 . the multiplier architecture in cyclone iv devices is the same as in the existing cyclone series devices. the embedded multiplier blocks can implement an 18 18 or two 9 9 multipliers in a single block. altera offers a complete suite of dsp ip including finite impulse response (fir), fast fourier transform (fft), and numerically controlled oscillator (nco) functions fo r use with the multiplier blocks. the quartus ? ii design software?s dsp builder tool integrates mathworks simulink and matlab design environments for a streamlined dsp design flow. f for more information, refer to the logic elements and logic array blocks in cyclone iv devices , memory blocks in cyclone iv devices , and embedded multipliers in cyclone iv devices chapters. table 1?7. m9k block data widths for cyclone iv device family mode data width configurations single port or simple dual port 1, 2, 4, 8/9, 16/18, and 32/36 true dual port 1, 2, 4, 8/9, and 16/18
chapter 1: cyclone iv fpga device family overview 1?9 cyclone iv device family architecture february 2013 altera corporation cyclone iv device handbook, volume 1 i/o features cyclone iv device i/o supports progra mmable bus hold, pr ogrammable pull-up resistors, programmable delay, prog rammable drive strength, programmable slew-rate control to optimize signal integrity, and hot socketing. cyclone iv devices support calibrated on-chip se ries termination (rs oct) or driver impedance matching (rs) for single-ended i/o standards. in cyclone iv gx devices, the high-speed transceiver i/os are located on the left side of the device. the top, bottom, and right sides can implement general-purpose user i/os. table 1?8 lists the i/o standards that cyclone iv devices support. the lvds serdes is implemented in the core of the device using logic elements. f for more information, refer to the i/o features in cyclone iv devices chapter. clock management cyclone iv devices include up to 30 global clock (gclk) networks and up to eight plls with five outputs per pll to provide robust clock management and synthesis. you can dynamically reconfigur e cyclone iv device plls in user mode to change the clock frequency or phase. cyclone iv gx devices support two types of plls: multipurpose plls and general- purpose plls: use multipurpose plls for clocking the tr ansceiver blocks. you can also use them for general-purpose clocking when they are not used for transceiver clocking. use general purpose plls for general-purpose applications in the fabric and periphery, such as external memory inte rfaces. some of the general purpose plls can support transceiver clocking. f for more information, refer to the clock networks and plls in cyclone iv devices chapter. external memory interfaces cyclone iv devices support sdr, ddr, ddr2 sdram, and qdrii sram interfaces on the top, bottom, and right sides of the device. cyclone iv e devices also support these interfaces on the left side of the device. interfaces may span two or more sides of the device to allow more flexible board design. the altera ? ddr sdram memory interface solution consists of a phy interfac e and a memory controller. altera supplies the phy ip and you can use it in conj unction with your own custom memory controller or an altera-provided memory controller. cyclone iv devices support the use of error correction coding (ecc) bits on ddr and ddr2 sdram interfaces. table 1?8. i/o standards support for the cyclone iv device family type i/o standard single-ended i/o lvttl, lvcmos, sstl, hstl, pci, and pci-x differential i/o sstl, hstl, lvpecl, blvds, lvds, mini-lvds, rsds, and ppds
1?10 chapter 1: cyclone iv fpga device family overview cyclone iv device family architecture cyclone iv device handbook, february 2013 altera corporation volume 1 f for more information, refer to the external memory interf aces in cyclone iv devices chapter. configuration cyclone iv devices use sram cells to store configuration data. co nfiguration data is downloaded to the cyclone iv device each time the device powers up. low-cost configuration options include the altera epcs family serial flash devices and commodity parallel flash configuration opti ons. these options provide the flexibility for general-purpose applications and the ability to meet specific configuration and wake-up time requirements of the applications. table 1?9 lists which configuration schemes are supported by cyclone iv devices. ieee 1149.6 (ac jtag) is supported on all transceiver i/o pins. all other pins support ieee 1149.1 (jtag) for boundary scan testing. f for more information, refer to the jtag boundary-scan testing for cyclone iv devices chapter. for cyclone iv gx devices to meet the pcie 100 ms wake-up time requirement, you must use passive serial (ps) configurat ion mode for the ep4cgx15/22/30 devices and use fast passive parallel (fpp) conf iguration mode for the ep4cgx30f484 and ep4cgx50/75/110/150 devices. f for more information, refer to the configuration and remote system upgrades in cyclone iv devices chapter. the cyclical redundancy check (crc) error detection feature during user mode is supported in all cyclone iv gx devices. for cy clone iv e devices, this feature is only supported for the devices with the core voltage of 1.2 v. f for more information about crc error detection, refer to the seu mitigation in cyclone iv devices chapter. high-speed transceivers (c yclone iv gx devices only) cyclone iv gx devices contain up to eight fu ll duplex high-speed transceivers that can operate independently. these blocks support multiple industry-standard communication protocols, as well as ba sic mode, which you can use to implement your own proprietary protocols. each tran sceiver channel has its own pre-emphasis and equalization circuitry, which you can set at compile time to optimize signal integrity and reduce bit error rates. transceiver blocks also support dynamic reconfiguration, allowing you to change data rates and protocols on-the-fly. table 1?9. configuration schemes for cyclone iv device family devices supported configuration scheme cyclone iv gx as, ps, jtag, and fpp (1) cyclone iv e as, ap, ps, fpp, and jtag note to table 1?9 : (1) the fpp configuration scheme is only supported by the ep4cgx30f 484 and ep4cgx50/75 /110/150 devices.
chapter 1: cyclone iv fpga device family overview 1?11 cyclone iv device family architecture february 2013 altera corporation cyclone iv device handbook, volume 1 figure 1?1 shows the structure of the cyclone iv gx transceiver. f for more information, refer to the cyclone iv transceivers architecture chapter. hard ip for pci express (c yclone iv gx devices only) cyclone iv gx devices incorporate a single ha rd ip block for 1, 2, or 4 pcie (pipe) in each device. this hard ip block is a co mplete pcie (pipe) protocol solution that implements the phy-mac layer, data link layer, and transaction layer functionality. the hard ip for the pcie (pipe) block supports root-port and end-point configurations. this pre-verified hard ip block reduces risk, design time, timing closure, and verification. yo u can configure the block with the quartus ii software?s pci express compiler, which guides you through the process step by step. f for more information, refer to the pci express compiler user guide . figure 1?1. transceiver channel for the cyclone iv gx device rx phase compensation fifo tx phase compensation fifo byte ordering byte deserializer byte serializer 8b10b decoder 8b10b encoder rate match fifo receive r channel pcs receive r channel pma word aligner rx_datain deserializer cdr t r ansmi tt e r channel pcs t r ansceive r channel pma tx_dataout serializer pci exp r ess ha r d ip fpga fab r ic pipe in t e r face
1?12 chapter 1: cyclone iv fpga device family overview reference and ordering information cyclone iv device handbook, february 2013 altera corporation volume 1 reference and ordering information figure 1?2 shows the ordering codes for cyclone iv gx devices. figure 1?3 shows the ordering codes for cyclone iv e devices. figure 1?2. packaging ordering information for the cyclone iv gx device family signature transceiver count package type package code operating temperature speed grade optional suffix indicates specific device options or shipment method gx : 3-gbps transceivers ep4c : cyclone iv 15 : 14,400 logic elements 22 : 21,280 logic elements 30 : 29,440 logic elements 50 : 49,888 logic elements 75 : 73,920 logic elements 110 : 109,424 logic elements 150 : 149,760 logic elements b : 2 c : 4 d : 8 f : fineline bga (fbga) n : quad flat pack no lead (qfn) fbga package type 14 : 169 pins 19 : 324 pins 23 : 484 pins 27 : 672 pins 31 : 896 pins qfn package type 11 : 148 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) 6 (fastest) 7 8 n : lead-free packaging es : engineering sample ep4c gx 30 c f 19 c 7 n member code family variant figure 1?3. packaging ordering information for the cyclone iv e device family signature gy package code operating temperature speed grade optional suffix indicates specific device options or shipment method e : enhanced logic/memory ep4c : cyclone iv 6 : 6,272 logic elements 10 : 10,320 logic elements 15 : 15,408 logic elements 22 : 22,320 logic elements 30 : 28,848 logic elements 40 : 39,600 logic elements 55 : 55,856 logic elements 75 : 75,408 logic elements 115 : 114,480 logic elements f : fineline bga (fbga) e : enhanced thin quad flat pack (eqfp) u : ultra fineline bga (ubga) m : micro fineline bga (mbga) fbga package type 17 : 256 pins 23 : 484 pins 29 : 780 pins eqfp package type 22 : 144 pins ubga package type 14 : 256 pins 19 : 484 pins mbga package type 8 : 164 pins 9 : 256 pins c : commercial temperature (t j = 0 c to 85 c) i : industrial temperature (t j = -40 c to 100 c) extended industrial temperature (t j = -40 c to 125 c) a : automotive temperature (t j = -40 c to 125 c) 6 (fastest) 7 8 9 n : lead-free packaging es : engineering sample l : low-voltage device ep4c e 40 f 29 c 8 n member code family variant
chapter 1: cyclone iv fpga device family overview 1?13 document revision history february 2013 altera corporation cyclone iv device handbook, volume 1 document revision history table 1?10 lists the revision history for this chapter. table 1?10. document revision history date version changes february 2013 1.7 updated table 1?3 , table 1?6 and figure 1?3 to add new device options and packages. october 2012 1.6 updated table 1?3 and table 1?4 . november 2011 1.5 updated ?cyclone iv device family features? section. updated figure 1?2 and figure 1?3. december 2010 1.4 updated for the quartus ii software version 10.1 release. added cyclone iv e new device package information. updated table 1?1, table 1?2, table 1?3, table 1?5, and table 1?6. updated figure 1?3. minor text edits. july 2010 1.3 updated table 1?2 to include f484 package information. march 2010 1.2 updated table 1?3 and table 1?6. updated figure 1?3. minor text edits. february 2010 1.1 added cyclone iv e devices in table 1?1, table 1?3, and table 1?6 for the quartus ii software version 9.1 sp1 release. added the ?cyclone iv device family speed grades? and ?configuration? sections. added figure 1?3 to include cyclone iv e device packaging ordering information. updated table 1?2, table 1?4, and table 1?5 for cyclone iv gx devices. minor text edits. november 2009 1.0 initial release.
1?14 chapter 1: cyclone iv fpga device family overview document revision history cyclone iv device handbook, february 2013 altera corporation volume 1

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